Hi all,

I'm new to FPGA and OpenCL programming, I'm trying to test the OpenCL SDSoC and SDAccel examples in my Zynq ZCU102 Ultrascale.
For example this https://github.com/Xilinx/SDSoC_Exam...aflow_func_ocl the compilation seems to work and generates the following directories tree:

Code :

For the compilation I used the Makefile provided ( https://github.com/Xilinx/SDSoC_Exam...c_ocl/Makefile ) with target hw and platform zcu102.
The problem is that when I try to run adder on Ultrascale, the whole board blocks after cl::enqueueTask invocation, and I can do anything else than rebooting the board. It seems very strange because this example works perfectly on ZedBoard but doesn't work on Ultrascale+.

I'm using XOCC compiler v2017.4 (installed with SDx toolkit) and zcu102.xpfm platform, and the board is Zynq Ultrascale+ HW-Z1-ZCU102 Revision C.2.

Could you give me some advices for solving this problem? unfortunately I don't have any ideas