Hi all,
I’m new to FPGA and OpenCL programming, I’m trying to test the OpenCL SDSoC and SDAccel examples in my Zynq ZCU102 Ultrascale.
For example this SDSoC_Examples/ocl/getting_started/dataflow_func_ocl at master · Xilinx/SDSoC_Examples · GitHub the compilation seems to work and generates the following directories tree:
sd_card
-adder
-BOOT.BIN
-image.ub
-libxilinxopencl.so
-README.txt
-adder.xclbin
-embedded_root
--runtime
---platforms
----driver
-----driver
------libxclzynqdrv.so
-init.sh
-platform_desc.txt
-zocl.ko
For the compilation I used the Makefile provided ( SDSoC_Examples/Makefile at master · Xilinx/SDSoC_Examples · GitHub ) with target hw and platform zcu102.
The problem is that when I try to run adder on Ultrascale, the whole board blocks after cl::enqueueTask invocation, and I can do anything else than rebooting the board. It seems very strange because this example works perfectly on ZedBoard but doesn’t work on Ultrascale+.
I’m using XOCC compiler v2017.4 (installed with SDx toolkit) and zcu102.xpfm platform, and the board is Zynq Ultrascale+ HW-Z1-ZCU102 Revision C.2.
Could you give me some advices for solving this problem? unfortunately I don’t have any ideas
Thanks