I find your description potentially misleading.
There’s not necessarily any “move” there. It is “source” because that stage of some command produces some data to the image\buffer the “destination” will later need.
The Execution dependency of the pipeline barrier is making sure the “source” stage (and any logically earlier stage) of any previously recorded command is executed before the “destination” stage (and any logically later stage) of any subsequently recorded command. Otherwise the data written by “source” does not necessarily exist yet when the “destination” needs it, because the “source” was not executed yet.
The raw Execution dependency does not cover Memory dependecies though. It is tricky, because we are not exposed to Memory dependecies in high-level programming languages, so it feels foreign. There is many underlying reasons to potentially need a Memory dependecy, but lets think of it in terms of a Cache hierarchy. The srcAccessMask
makes sure the needed data is flushed from the source. The dstAccessMask
makes sure the necessary data is invalidated
for the destination.
[HR][/HR]
As for the pipelines, there are several types of them:
For the graphics pipeline, the following stages occur in this order:
VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
For the compute pipeline, the following stages occur in this order:
VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
For the transfer pipeline, the following stages occur in this order:
VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
VK_PIPELINE_STAGE_TRANSFER_BIT
VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
For host operations, only one pipeline stage occurs, so no order is guaranteed:
VK_PIPELINE_STAGE_HOST_BIT
As you can see the transfer is different pipeline than the graphics. So they do not “insert themself” in any way.