Apologies if I'm missing something, but I don't get table 3.17.1 in this spec. Shouldn't there be 4 x 8bit texels in the PALETTE8_xxx diagram rather than 8 x 4bit?

Also, I humbly submit that showing the packing of 8bit texels into a 32bit word is misleading in any case - if I packed a word as shown and stored it to memory, wouldn't the result depend on CPU endianness? Why does 32bit packing come into this at all?